JAIST Repository >
b. 情報科学研究科・情報科学系 >
b10. 学術雑誌論文等 >
b10-1. 雑誌掲載論文 >
このアイテムの引用には次の識別子を使用してください:
http://hdl.handle.net/10119/8520
|
タイトル: | Novel Register Sharing in Datapath for Structural Robustness against Delay Variation |
著者: | INOUE, Keisuke KANEKO, Mineo IWAGAKI, Tsuyoshi |
キーワード: | datapath synthesis delay variation register assignment setup and hold constraints |
発行日: | 2008-04-01 |
出版者: | 電子情報通信学会 |
誌名: | IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences |
巻: | E91-A |
号: | 4 |
開始ページ: | 1044 |
終了ページ: | 1053 |
DOI: | 10.1093/ietfec/e91-a.4.1044 |
抄録: | As the feature size of VLSI becomes smaller, delay variations become a serious problem in VLSI. In this paper, we propose a novel class of robustness for a datapath against delay variations, which is named structural robustness against delay variation (SRV), and propose sufficient conditions for a datapath to have SRV. A resultant circuit designed under these conditions has a larger timing margin to delay variations than previous designs without sacrificing effective computation time. In addition, under any degree of delay variations, we can always find an available clock frequency for a datapath having SRV property to operate correctly, which could be a preferable characteristic in IP-based design. |
Rights: | Copyright (C)2008 IEICE. Keisuke INOUE, Mineo KANEKO, Tsuyoshi IWAGAKI, IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, E91-A(4), 2008, 1044-1053. http://www.ieice.org/jpn/trans_online/ |
URI: | http://hdl.handle.net/10119/8520 |
資料タイプ: | publisher |
出現コレクション: | b10-1. 雑誌掲載論文 (Journal Articles)
|
このアイテムのファイル:
ファイル |
記述 |
サイズ | 形式 |
11136.pdf | | 328Kb | Adobe PDF | 見る/開く |
|
当システムに保管されているアイテムはすべて著作権により保護されています。
|