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Master of Science（Information Science） >
H25) (Jun.2013 - Mar.2014 >
Please use this identifier to cite or link to this item:
https://hdl.handle.net/10119/12013
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| Title: | RTLとゲートレベルを混在させた最適な論理回路設計に関する研究 |
| Authors: | 張, 之飛 |
| Authors(alternative): | ちょう, しひ |
| Keywords: | 論理回路
Logic Circuits |
| Issue Date: | Mar-2014 |
| Description: | Supervisor:田中清史
情報科学研究科
修士 |
| Title(English): | A Study on Optimal Logic Circuits Combining RTL and Gate-Level Designs |
| Authors(English): | ZHANG, ZHIFEI |
| Language: | jpn |
| URI: | https://hdl.handle.net/10119/12013 |
| Appears in Collections: | M-IS. 2013年度(H25) (Jun.2013 - Mar.2014)
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