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Doctor of Philosophy（Information Science） >
R07) (Jun.2025 - Mar.2026 >
Please use this identifier to cite or link to this item:
https://hdl.handle.net/10119/20594
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| Title: | 完全パイプライン型2LAL断熱論理回路の設計自動化および最適化 |
| Authors: | 潮田, 裕也 |
| Authors(alternative): | うしおだ, ゆうや |
| Keywords: | adiabatic logic
reversible computing
Two-Level Adiabatic Logic (2LAL)
early decompute scheduling
buffer minimization
integer linear programming
stable set problem
pipeline rescheduling
energy-area trade-off
low-power VLSI
sustainable computing |
| Issue Date: | Mar-2026 |
| Description: | Supervisor: 田中 清史
先端科学技術研究科
博士 |
| Title(English): | Design automation and optimization of fully pipelined 2LAL adiabatic logic circuits |
| Authors(English): | USHIODA, YUYA |
| Language: | eng |
| URI: | https://hdl.handle.net/10119/20594 |
| Academic Degrees and number: | 甲第1633号 |
| Degree-granting date: | 2026-03-25 |
| Degree name: | 博士 (情報科学) |
| Degree-granting institutions: | 北陸先端科学技術大学院大学 |
| Appears in Collections: | D-IS. 2025年度(R07) (Jun.2025 - Mar.2026)
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Files in This Item:
| File |
Description |
Size | Format |
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| abstract.pdf | 要旨 | 51Kb | Adobe PDF | View/Open | | paper.pdf | 本文 | 8369Kb | Adobe PDF | View/Open | | summary.pdf | 内容の要旨及び論文審査の結果の要旨 | 331Kb | Adobe PDF | View/Open |
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